A Hardware-Oriented Concurrent Test Zone Search Algorithm for High-Efficiency Video Coding

Abstract

High-Efficiency Video Coding (HEVC) [1-5] is the latest video coding standard, in which the compression performance is double that of its predecessor, the H.264/AVC standard while the video quality remains unchanged. In HEVC, the Test Zone (TZ) search algorithm is widely used for integer motion estimation because it effectively searches the good-quality motion vector with a relatively small amount of computation. However, the complex computation structure of the TZ search algorithm makes it difficult to implement it in hardware. This work proposes a new integer motion estimation algorithm which is designed for hardware execution by modifying the conventional TZ search to allow parallel motion estimations of all prediction unit (PU) partitions. The algorithm consists of the three phases of zonal, raster and refinement searches. At the beginning of each phase, the algorithm obtains the search points required by the original TZ search for all PU partitions in a coding unit (CU). Then, all redundant search points are removed prior to the estimation of the motion costs and the best search points are then selected for all PUs. Compared to the conventional TZ search algorithm, experimental results show that the proposed algorithm significantly decreases the Bjøntegaard-Delta bitrate (BD-BR) by 0.84%, and it also reduces the computational complexity by 54.54%.