Capacitance–Voltage Characterization of Tunnel Field Effect Transistors with a Si/SiGe Heterojunction

Abstract

A Si capping layer on a SiGe channel is essential to improve the interface properties between the SiGe channel and the gate insulator. Thus, devices with a Si capping layer should be analyzed to understand their electrical characteristics. In this thesis, a strained Si/SiGe heterojunction TFET is investigated via capacitance–voltage measurements, which are rapid and non-destructive. The C–V analysis method in a strained Si/SiGe heterojunction TFET is improved through TCAD simulations. Through a C–V analysis, important parameters pertaining to devices, such as the layer thicknesses and threshold voltages, can be extracted.