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Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement
Cited 2 time in
Web of Science
Cited 10 time in Scopus
- Authors
- Issue Date
- 2016-08
- Publisher
- Japan Soc of Applied Physics
- Citation
- Applied Physics Express, Vol.9 No.8, pp.084201-084201
- Abstract
- One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention time. In this letter, a 1T-DRAM cell with two separated asymmetric gates was fabricated and evaluated to improve sensing margin and retention characteristics. It was observed that significantly enhanced sensing margin and retention time over 1 s were obtained using a negatively biased second gate and trapped electrons in the nitride layer because of increased hole capacity in the floating body. These findings indicate that the proposed device could serve as a promising candidate for overcoming retention issues of 1T-DRAM cells. (C) 2016 The Japan Society of Applied Physics
- ISSN
- 1882-0778
- Language
- English
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