Methodology for Solving Timing Closure Problem by Utilizing Adjustable Delay Clock Buffers

Abstract

As clock timing is closely related to the performance of synchronous systems, many synthesis techniques were suggested to optimize clock distribution networks. Especially, meeting clock skew constraints is one of the most important objectives that should be achieved for successful operation of the design. Meanwhile, multiple power mode designs made the clock timing problem harder to tackle due to the dynamic delay change caused by varying supply voltages. Inserting adjustable delay buffers (ADBs) on the clock tree and controlling its delay can be a solution to the problem. However, because ADBs require non-negligible area and control overhead, it should be carefully inserted to minimize the number of ADBs. This work provides solutions to the ADB minimization problem under the environment of multiple power modes in which the clock path delay varies as power mode changes. Precisely, (1) an O(n log n) time algorithm that optimally solves the problem under clock skew bounds and (2) a graph based algorithm which supports useful skew scheduling are proposed, along with (3) their practical extensions, such as supporting discrete delay values and reducing more ADBs by integrating buffer sizing scheme. The experimental results showed that proposed ADB allocation algorithms under constant clock skew bound and useful skew constraints allocated 13.5% and 23.3% less number of ADBs on average, respectively, compared to the best known ADB allocation algorithm under the same constraints.