Studies on Resonant Clock Network Synthesis and Design Technology Co-Optimization Framework

Abstract

In modern VLSI design, there exists a tendency of integrating various com-<br/> ponents including microprocessors, memory blocks, I/O interface and peripher-<br/> als, which can be classified into digital, analog and mixed-signal by their oper-<br/> ation. In general, digital blocks are implemented as synchronous circuits which<br/> operate in sync with the global clock signal and occupy majority portion of<br/> the total chip in terms of area and power consumption. Therefore, saving of<br/> power consumption caused by the clock network is important in achieving a<br/> low-power design. On the other hand, in development of advanced technology<br/> nodes, the sequential product development flow faces a challenge of difficulty in<br/> overall product optimization due to increased TAT (turn-around time) between<br/> design and process development. To resolve this, a DTCO (Design Technology<br/> Co-Optimization) is introduced. Impact of process development to an overall<br/> product can be predicted and analyzed through standard cells which occupy a<br/> majority of digital blocks up to 60%.<br/> First, by introducing on-chip inductors, LC resonance is adopted to reduce<br/> excessive power consumption of clock distribution network. In the presence of<br/> DVFS (Dynamic Voltage/Frequency Scaling), a widely used low power tech-<br/> nique in modern VLSI design, a methodology of synthesizing resonant clock<br/> network is proposed to achieve acceptable power reduction while minimizing<br/> area overhead of inductors and clock driving buffers. Experiments of several<br/> benchmarks show the effectiveness of the proposed method.<br/> Second, a standard cell layout generator is developed to produce cell lay-<br/> outs of which quality is comparable to industrys manually optimized one. The<br/> generator adopts advanced process technology including FinFET transistors,<br/> DP (double patterning) lithography, and complex design rules. In addition, a<br/> DTCO framework which uses the proposed standard cell generator as a core<br/> engine is developed for an effective DTCO work. By experiments using the pro-<br/> posed framework, it is shown that standard cells are generated successfully and<br/> optimization point between design and process can be explored.