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Optimizing Heterogeneous System Architecture Through Memory Throttling : 메모리Throttling을 통한 이기종 시스템 구조 최적화 방법
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Bernhard Egger | - |
dc.contributor.author | 제신이 | - |
dc.date.accessioned | 2018-12-03T01:48:58Z | - |
dc.date.available | 2018-12-03T01:48:58Z | - |
dc.date.issued | 2018-08 | - |
dc.identifier.other | 000000151707 | - |
dc.identifier.uri | https://hdl.handle.net/10371/144024 | - |
dc.description | 학위논문 (석사)-- 서울대학교 대학원 : 공과대학 컴퓨터공학부, 2018. 8. Bernhard Egger. | - |
dc.description.abstract | CPU와 GPU core들의 장점을 최대한 활용하고, 자원들을 최대한 사용하기 위
해,최근 CPU와 GPU core들이 한 실리콘 칩에 함께 있는 이기종 시스템 구조 (Heterogeneous System Architecture)가 제안되었다. 비록 통합된 구조가 CPU 와 GPU의 통신을 단순화하고, 모든 Computing Unit들이 같은 메모리 공간으로 맵핑되지만, 새로운 문제점들이 발생한다. CPU와 GPU가 공유하는 메모리 대역 폭은 제한되어 있지만, GPU의 request들이 상당히 많기 때문에, 대부분의 메모리 대역폭은 GPU request들에 의해서 차지하게 된다. HSA에서는 Co-running 어플 리케이션이 실행될 때, CPU request들은 GPU request들에 의해서 우선순위를 빼앗기게 되고 성능저하로 이어진다. 본 논문에서는 HSA를 memory throttling 으로 CPU와 GPU request들을 적절한 순서로 진행하게하여, 최적화 하는 새로운 방법을 제안한다. Request들의 타입에 따라서 스케쥴링할 수 있는 비율은 설정 가능하다. 우리는 HSA 시뮬레이터인 GEM5-GPU에서 실험하였고 결과적으로, 제안한 방법을 적용하여 어플리케이션의 수행시간을 최대 23%만큼 줄였다. 메 모리에서CPU와 GPU의 request들의 대기시간또한 ratio를 변경함으로써 명확한 차이를 보였다. | - |
dc.description.abstract | In order to fully utilize the resources and advantages of CPU and GPU cores,
Heterogeneous System Architectures (HSA) that integrate CPU and GPU cores on the same silicon chip have been proposed recently. The advantages of this fusion architecture are simplified the communication between the CPU and the GPU and global shared memory for all computing units | - |
dc.description.abstract | however, new problems
arise as well. The shared memory bandwidth is limited, but the number of GPU requests is so substantial that almost the full memory bandwidth can be oc cupied by GPU requests. The performance of an application that utilizes both CPU and GPU cores on a HSA can be degraded because the CPUs memory requests are not be processed in time. In this thesis, we propose a new method ology aiming at optimizing HSAs through memory throttling so that CPU and GPU requests can be processed with acceptable latencies. The ratio of schedul ing different types requests is configurable. We implement and evaluate the proposed methodology on a HSA simulator called Gem5-GPU. The evaluation of our approach shows that the execution time of several benchmarks can be reduced by up to 23% on average through applying the proposed methodology. The latency of CPU and GPU requests is also significantly reduced for different distribution ratios. | - |
dc.description.tableofcontents | Chapter 1 Introduction 1
Chapter 2 Background 5 2.1 The Heterogeneous System Architecture 5 2.1.1 Features 6 2.1.2 Memory Model 7 2.2 Memory bottleneck problem 7 2.3 Related work 9 Chapter 3 Introduction of Gem5-GPU 12 3.1 Overview 12 3.2 Reasons for selecting Gem5-GPU 14 3.2.1 Other HSA simulators 14 3.2.2 Why Gem5-GPU 15 3.3 Structure and memory model 16 3.4 Interest in Gem5-GPU 18 Chapter 4 Methodology 19 4.1 Analysis of the Gem5-GPU memory controller 19 4.1.1 Components 21 4.1.2 Receiving a request 21 4.1.3 Processing a request 22 4.2 Adding tags 23 4.2.1 Tagging at the source 24 4.2.2 Tagging in the sequencers 25 4.2.3 Tagging in the cache coherence protocol 25 4.3 Scheduling 25 4.3.1 Dividing the global queue 26 4.3.2 Scheduling 30 Chapter 5 Evaluation 33 5.1 Applications 33 5.2 Experimental setups and results 34 5.3 Limits of the proposed approach 38 Chapter 6 Conclusion and Future Work 41 6.1 Conclusion 41 6.2 Future Work 42 Bibliography 42 요약 47 | - |
dc.format | application/pdf | - |
dc.format.medium | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject.ddc | 621.39 | - |
dc.title | Optimizing Heterogeneous System Architecture Through Memory Throttling | - |
dc.title.alternative | 메모리Throttling을 통한 이기종 시스템 구조 최적화 방법 | - |
dc.type | Thesis | - |
dc.description.degree | Master | - |
dc.contributor.affiliation | 공과대학 컴퓨터공학부 | - |
dc.date.awarded | 2018-08 | - |
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