Investigation of Vertical Type Single-Electron Transistor with Sidewall Spacer Quantum Dot

Abstract

Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region. However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works. In this paper, we propose a new SET structure that is fabricated on a bare wafer, and simpler fabrication process than those reported previously. With this structure, QD size is reduced without complicated methods, so the characteristic of the device is clearer than previous works as shown in simulation results at RT. Using this device, we propose the inverter with two SETs that have different gate oxide thicknesses, and we show the characteristics with SIMON simulator. With this scheme, we show the possibility that can be fabricated other logic circuits as well as inverter.