Design Methodology of Reliable Clock Networks Based on Adjustable Delay Buffers

Abstract

Clock skew constraint satisfaction is one of the most important tasks in the clock network design, especially for the tree based clock structure. However, satisfying clock skew constraint is almost impossible by using traditional clock tree synthesis techniques when the clock tree is designed under multiple power mode environments. Recently, it is shown that using adjustable delay buffer (ADB) whose delay can be tuned dynamically can be an alternative solution to the clock skew optimization problem under multiple power mode environments. However, existing works on allocating ADBs under multi-voltage mode designs is not optimal and cannot be directly applied to real implementation because almost all researches are based on ideal assumption of ADB. This work provides a complete solution to the problem of clock skew minimization using ADBs under multiple power modes, supporting its practical applicability. We first propose a linear-time optimal algorithm that simultaneously solves the problems of computing (1) the minimum number of ADBs to be used, (2) the location at which each ADB is to be placed, and (3) the delay value of each ADB to be assigned to each power mode. Then, we propose a heuristic algorithm and new ADB structure to resolve the timing violations possibly incurred due to the application of the ADB allocation solution derived under the ideal assumption. Through a set of diverse and thorough experiments, we are able to confirm that the number of ADBs can be reduced by 9.27% on average under ideal assumptions and the violations induced by the ideal assumptions can be perfectly removed with small overhead by using our proposed ADB structure and algorithm.