PCRAM controller의 hardware prefetcher를 위한 data buffer 최적화

Abstract

본 논문에서는 PCRAM based storage의 cache buffer 성능 향상을 위한 prefetcher 구조에 대한 연구를 수행한다. Hdd, Nand-SSD를 위한 일반적인 software prefetcher가 아닌 PCRAM hard-wired controller를 위한 경량화된 hardware prefetching 구조를 제안함으로서 NVM stroage cache buffer의 최적화를 수행한다. 이 때 hardware prefetcher의 implementation시 단점으로 부각되는 history buffer의 area overhead, prefetching algorithm의 hardware complexity를 개선하기 위해 application id polling과 address boundary detector를 이용한 필터 구성으로 history buffer를 경량화하였다. application id poller는 단위 시점에서의 populated application id를 선정하고 해당 appication id의 cache miss address만을 sequential boundary detector로 인가한다. Sequential boundary detector는 miss address의 sequentiality를 detect하여 history buffer에 기록하고 이를 바탕으로 유형별 prefetch request를 생성한다 Real-life storage workload로 controller의 average latency를 측정하였고, 약 14%의 read latency개선으로 동일 성능 필요 cache buffer size의 50%만을 필요케끔 cache size가 최적화 됨을 확인하였다

In this paper, we study the prefetcher structure to improve the cache buffer performance of PCRAM based storage. We perform optimization of the NVM stroage cache buffer by proposing a lightweight hardware prefetching structure for PCRAM hard-wired controller, not a general software prefetcher for HDD and Nand-SSD. At this time, in order to improve the area overhead of the history buffer and hardware complexity of the prefetching algorithm, which is a drawback when implementing the hardware prefetcher, the history buffer is lightened by configuring a filter using application id polling and sequential address boundary detector. The application id poller selects the populated application id at the unit time point and applies only the cache miss address of the application id to the sequential boundary detector. Sequential boundary detector detects the sequentiality of miss addresses, records them in the history buffer, and creates prefetch requests for each type based on this. The average latency of the controller was measured with a real-life storage workload, and it was confirmed that the cache size was optimized so that only 50% of the cache buffer size required the same performance by improving the read latency of about 14%