Effects of Pillar Conditions on DC/AC Characteristics of Tunnel Field-effect Transistor with Vertical Structures

Abstract

To investigate the effects of various pillar conditions such as pillar thickness (T-pillar), pillar height (T-si), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFETvs) and AC switching characteristics of TFETvs inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the T-pillar is thicker, 2) the T-si is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (C-GD)-gate voltage (V-G) curve becomes positive-shifted due to the weaker controllability of V-G on the drain-side channel. Through the transient responses of TFETvs inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted C-GD-V-G curve caused by the weaker V-G controllability on the drain-side channel.