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Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology
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- Authors
- Issue Date
- 2020-06
- Publisher
- IEEE
- Citation
- 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, p. 9265089
- Abstract
- In this paper, key contributors to local variability of sub-7nm FinFET has been identified in various operating environments. Through a comprehensive analysis, different root-cause for high and low temperature region have been revealed and confirmed by advanced Si wafer for the first time. Moreover, a local variation-aware transistor was successfully demonstrated to reduce sigma V-min distribution by 0.5x and 0.3x at cold temperature.
- ISSN
- 0743-1562
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