Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot- carrier Stress Bias Conditions

Abstract

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (triangle L-ch) and threshold voltage shift (triangle V-th). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.