FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning

Abstract

To understand how the human brain works, neuroscientists heavily rely on brain simulations which incorporate the concept of time to their operating model. In the simulations, neurons transmit their signals through synapses whose weights change over time and by the activity of the associated neurons. Such changes in synaptic weights, known as learning, are thought to contribute to memory, and various learning rules exist to model different behaviors of the human brain. Due to the diverse neurons and learning rules, neuroscientists perform the simulations using highly programmable general-purpose processors. Unfortunately, the processors greatly suffer from the high computational overheads of the learning rules. As an alternative, brain simulation accelerators achieve orders of magnitude higher performance; however, they have limited flexibility and cannot support the diverse neurons and learning rules. In this paper, we present FlexLearn, a flexible on-chip learning engine to enable fast and highly efficient brain simulations. FlexLearn achieves high flexibility by supporting diverse biologically plausible sub-rules which can be combined to simulate various target learning rules. To design FlexLearn, we first identify 17 representative sub-rules which adjust the synaptic weights in different manners. Then, we design and compact the specialized datapaths for the subrules and identify dependencies between them to maximize parallelism. After that, we present an example flexible brain simulation processor by integrating the datapaths with the state-of-the-art flexible digital neuron and existing accelerator to support end-to-end simulations. Our evaluation using a 45-nm cell library shows that the 128-core brain simulation processor prototype with FlexLearn greatly improves the harmonic mean per-area performance and the energy efficiency by 30.07x and 126.87x, respectively, over the server-class CPU. The prototype also achieves the harmonic mean per-area speedup of 1.41x over the current state-of-the-art 128-core accelerator which supports programmable learning rules.