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A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hwang, Jeongho | - |
| dc.contributor.author | Choi, Hong-Seok | - |
| dc.contributor.author | Do, Hyungrok | - |
| dc.contributor.author | Jeong, Gyu-Seob | - |
| dc.contributor.author | Koh, Daehyun | - |
| dc.contributor.author | Park, Kwanseo | - |
| dc.contributor.author | Kim, Sungwoo | - |
| dc.contributor.author | Jeong, Deog-Kyoon | - |
| dc.date.accessioned | 2022-11-11T08:07:08Z | - |
| dc.date.available | 2022-11-11T08:07:08Z | - |
| dc.date.created | 2022-10-20 | - |
| dc.date.issued | 2019-06 | - |
| dc.identifier.citation | 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C268-C269 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/187043 | - |
| dc.description.abstract | This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm(2). | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.23919/VLSIC.2019.8777952 | - |
| dc.citation.journaltitle | 2019 SYMPOSIUM ON VLSI CIRCUITS | - |
| dc.identifier.wosid | 000531736500093 | - |
| dc.identifier.scopusid | 2-s2.0-85073898594 | - |
| dc.citation.endpage | C269 | - |
| dc.citation.startpage | C268 | - |
| dc.description.isOpenAccess | N | - |
| dc.contributor.affiliatedAuthor | Do, Hyungrok | - |
| dc.contributor.affiliatedAuthor | Jeong, Deog-Kyoon | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
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