In-memory Computing based on Two Anti-Parallel Bipolar Memristors for Beyond von-Neumann Architecture

Abstract

As technologies for artificial intelligence, big data, and the internet of things have been developing, the demand for the data-centric computation paradigm is increasing. The number of data growth is expected to be 181 zettabytes by 2025. Accordingly, the memory bottleneck exacerbates as the memory and processor are separately located in the von Neumann architecture. In order to resolve the bottleneck, many methodologies, including hybrid memory cube and high bandwidth memory, are proposed. Despite the possible improvement, the eventual limitation is expected as the data path between memory and processor exists and would be the critical path in computation. The discovery of a resistive switching memory named memristor, or resistive random-access memory−having nonvolatility, low power, high scalability, and fast switching− is the milestone that in-memory computing is possible, which removes the data path between the processor and memory. In other words, the memory bottleneck can be relieved significantly. The in-memory computing using memristors can be divided into two categories of stateful logic and sequential logic; indeed, there is another type called memristor ratioed logic but not considered here for simplicity. The stateful logic uses resistance forms of inputs and outputs, whereas the voltage form of inputs and resistance form of outputs are utilized in sequential logic. Many in-memory computing gates have been reported based on the stateful logic family due to the efficient implementation is possible using logic cascading, which is outputs of the previous logic gate can be used in inputs of the next logic gates, reducing the latency and area. Thus, many researchers have focused on the spatiotemporal cost in logic design. However, the implementation of stateful logic must be carefully considered due to the presence of voltage stress on the memristor in logic operation. Herein, the universal nomenclature for the in-memory computing gate is introduced for clarity. Then, a stateful logic family of two anti-parallel memristors with a series resistor is proposed that can operate IMP, RIMP, AND, and TF functions, defined as APMR-two-2(IMP, RIMP, AND, TF) logic gates. From the experimental demonstration after the optimization, over-set and over-current issues occur in the case of AND and TF functions, inducing infeasible implementation. Thus, the solution is proposed by altering the logic family from stateful logic to sequential logic in the same primitive circuit structure, which results in different basic logic operations, XOR, RIMP, and IMP. Consequently, APMR-two-2(XOR, RIMP, IMP) gates are operated within the optimized region without having the over-set or over-current issues. In addition, the cascading problem of sequential logic from the discrepancy between different forms of inputs and outputs is resolved by the newly proposed domain-specific logic gate for the XOR logic operation, named APMR-three-4XOR gate. This enables the logic cascading of the XOR logic function, which significantly improves the latency in in-memory computing since the function is high-latency-cost in general. Utilizing its CBA compatibility with other in-memory computing logic gates, an n-bit full adder of the arithmetic logic unit is implemented. Then, the adder is utilized further to implement an n-bit full subtractor, ripple-carry full adder-subtractor, and n × n multiplier, which results in lower latency by 30.1 % and area cost by 34.2 % compared to the state-of-art memristive ripple carry adder using other in-memory computing gates. Furthermore, the normalized device stress factor is introduced to determine the over-set or over-current issues, demonstrating that the proposed logic gates are more reliable than other gates. Consequently, other applications related to XOR logic operation will be demonstrated with low device-stress cost and latency.

인공지능, 빅데이터, IoT 등의 기술 발전에 따라 점차 데이터의 양이 기하급수 적으로 증가 하였고, 앞으로도 증가될 전망이다. 이에, 메모리와 프로세서가 분리된 기존 폰노이만 컴퓨팅 구조에서의 메모리 병목현상이 심화되고 있으며, 이를 해결하기 위해 다양한 방법론이 제시되었다. 그 중 효율적인 방법으로 저항변화메모리를 이용해서 컴퓨팅 구조를 변경하는 방법이 제안되었다. 즉, 메모리 내부에서 계산을 동시에 하는 인메모리 컴퓨팅 기술을 이용하여, 병목현상을 해결할 수 있으며, 동시에 에너지 효율적인 연산을 수행할 수 있다. 인메모리 컴퓨팅은 크게 두가지로 입력과 출력의 저항 성분으로 형태가 같은 stateful logic 과 입출력의 형태가 다른 sequential logic 으로 분류된다. 2010년에 처음 로직 게이트가 제안된 후, 많은 효율적인 인메모리 로직 게이트들이 제안되었으나, 게이트를 설계할 때, 에너지, 속도, 면적 이외로 고려가 되어야 할 중요한 재료적인 인자들이 무시 되어왔다. 본 연구에서는, 기존 stateful logic 방식으로 anti-parallel하게 연결된 두 멤리스터에 대해 로직게이트를 설계하였을 때, 새로운 로직게이트들을 제안하였으며, 기존 로직 설계방식으로 실제 로직 회로를 공정을 통해 제작 했을 때 재료적으로 발생할 수 있는 문제점들 대해 다루었다. 이를 해결하기 위해 sequential logic 방식으로 로직 설계를 어떻게 수정하여 좀 더 안정적이고 효율적인 로직게이트들을 제안한다. 추가적으로, 입출력 형태가 다른 것을 보정하기위한 새로운 알고리즘을 제안하였으며, 이를 이용하여, 가산기, 감산기, 가감산기, 곱셈기들을 제작하여 기존에 제안된 가장 빠른 로직게이트들 대비 가감산기 기준 속도 측면에서 30.1% 그리고 스케일 측면에서 34.2% 의 향상을 보여주었다. 추가적으로, 로직게이트의 안정성을 판단하는 척도로 κ 인자를 새로 제안하였으며, 이를 활용하여, 전압을 가했을 때, 안정적으로 동작할 수 있음을 제안하였다. 추가적으로 XOR 로직 동작 속도를 가속시켜, 이를 활용하면 좀 더 복잡한 연산에 응용될 가능성을 제안하였다.