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Making DRAM Stronger Against Row Hammering
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Son, M. | - |
dc.contributor.author | Park, H. | - |
dc.contributor.author | Ahn, J. | - |
dc.contributor.author | Yoo, S. | - |
dc.date.accessioned | 2023-06-27T06:38:22Z | - |
dc.date.available | 2023-06-27T06:38:22Z | - |
dc.date.created | 2023-06-19 | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Proceedings - Design Automation Conference, Vol.Part 128280, p. 55 | - |
dc.identifier.issn | 0146-7123 | - |
dc.identifier.uri | https://hdl.handle.net/10371/192905 | - |
dc.description.abstract | Modern DRAM suffers from a new problem called row hammering. The problem is expected to become more severe in future DRAMs mostly due to increased inter-row coupling at advanced technology. In order to address this problem, we present a probabilistically managed table (called PRoHIT) implemented on the DRAM chip. The table keeps track of victim row candidates in a probabilistic way and, in case of auto-refresh, the topmost entry is additionally refreshed thereby mitigating the row hammering problem. Our experiments with PARSEC benchmark and synthetic traces show that PRoHIT outperforms the state-of-The-Art method, PARA, by 35.7% (PARSEC) in terms of the reduction ratio of row-hammer cases. Our proposed method also shows constantly superior performance to PARA for synthetic traces. © 2017 ACM. | - |
dc.language | 영어 | - |
dc.publisher | Proceedings - Design Automation Conference | - |
dc.title | Making DRAM Stronger Against Row Hammering | - |
dc.type | Article | - |
dc.citation.journaltitle | Proceedings - Design Automation Conference | - |
dc.identifier.scopusid | 2-s2.0-85023594788 | - |
dc.citation.startpage | 55 | - |
dc.citation.volume | Part 128280 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Yoo, S. | - |
dc.description.journalClass | 1 | - |
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