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3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Hunjun | - |
dc.contributor.author | Kim, Minseop | - |
dc.contributor.author | Min, Dongmoon | - |
dc.contributor.author | Kim, Joonsung | - |
dc.contributor.author | Back, Jongwon | - |
dc.contributor.author | Yoo, Honam | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Kim, Jangwoo | - |
dc.date.accessioned | 2023-10-30T01:48:19Z | - |
dc.date.available | 2023-10-30T01:48:19Z | - |
dc.date.created | 2023-08-23 | - |
dc.date.created | 2023-08-23 | - |
dc.date.created | 2023-08-23 | - |
dc.date.issued | 2022 | - |
dc.identifier.citation | Proceedings of the Annual International Symposium on Microarchitecture, MICRO, Vol.2022-October, pp.1359-1376 | - |
dc.identifier.issn | 1072-4451 | - |
dc.identifier.uri | https://hdl.handle.net/10371/195872 | - |
dc.description.abstract | The crossbar structure of the nonvolatile memory enables highly parallel and energy-efficient analog matrix-vector-multiply (MVM) operations. To exploit its efficiency, existing works design a mixed-signal deep neural network (DNN) accelerator, which offloads low-precision MVM operations to the memory array. However, they fail to accurately and efficiently support the low-precision networks due to their naive ADC designs. In addition, they cannot be applied to the latest technology nodes due to their premature RRAM-based memory array. In this work, we present 3D-FPIM, an energy-efficient and robust mixed-signal DNN acceleration system 3D-FPIM is a full-stack 3D NAND flash-based architecture to accurately deploy low-precision networks. We design the hardware stack by carefully architecting a specialized analog-to-digital conversion method and utilizing the three-dimensional structure to achieve high accuracy, energy efficiency, and robustness. To accurately and efficiently deploy the networks, we provide a DNN retraining framework and a customized compiler. For evaluation, we implement an industry-validated circuit-level simulator. The result shows that 3D-FPIM achieves an average of 2.09x higher performance per area and 13.18x higher energy efficiency compared to the baseline 2D RRAM-based accelerator. | - |
dc.language | 영어 | - |
dc.publisher | Proceedings of the Annual International Symposium on Microarchitecture, MICRO | - |
dc.title | 3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/MICRO56248.2022.00093 | - |
dc.citation.journaltitle | Proceedings of the Annual International Symposium on Microarchitecture, MICRO | - |
dc.identifier.wosid | 000886530600079 | - |
dc.identifier.scopusid | 2-s2.0-85141709457 | - |
dc.citation.endpage | 1376 | - |
dc.citation.startpage | 1359 | - |
dc.citation.volume | 2022-October | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Lee, Jong-Ho | - |
dc.contributor.affiliatedAuthor | Kim, Jangwoo | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | DNN | - |
dc.subject.keywordAuthor | 3D NAND Flash | - |
dc.subject.keywordAuthor | mixed-signal accelerator | - |
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