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메모리 인터페이스용 다중 위상 DC-DC 변환기 설계 : Design of Multi-phase DC-DC Converter in Memory Interface

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dc.contributor.advisor정덕균-
dc.contributor.author전주영-
dc.date.accessioned2023-11-20T04:23:05Z-
dc.date.available2023-11-20T04:23:05Z-
dc.date.issued2023-
dc.identifier.other000000177702-
dc.identifier.urihttps://hdl.handle.net/10371/196461-
dc.identifier.urihttps://dcollection.snu.ac.kr/common/orgView/000000177702ko_KR
dc.description학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 8. 정덕균.-
dc.description.abstractABSTRACT

메모리 인터페이스용 다중 위상 DC-DC 변환기 설계

본 논문에서는 메모리 인터페이스용 고전압 고전류를 위한 multi-phase DC-DC Buck 컨버터를 제안한다. 최근 개인 휴대용 device 및 laptop 등을 통하여 IT device를 통해 사용되는 data memory의 양이 기하급수적으로 증가함에 따라 cloud server의 증설이 되고 있으며 이에 따라 모든 시스템에 효율적이고 안정적인 Power의 공급은 필수적이다. 이러한 요구 조건을 만족하기 위하여 많은 구동 방식의 DC-DC 컨버터가 연구되고 있다.
제안하는 multi-phase DC-DC buck 컨버터는 고전류를 4-phase 로 각각 균등 분할하여 Power MOSFET 이 turn-on 될 때에 Ron 저항으로 인하여 발생할 수 있는 power loss를 줄이고, current balancing 회로를 통하여 각 phase가 synchronous 하게 동작을 할 수 있도록 설계하였다. 또한, memory device 가 순간적으로 구동하여 출력단에서 발생될 수 있는 voltage droop의 load transient response도 출력단에서의 즉각적인 current feedback을 통하여 빠르게 대응을 할 수가 있다.
본 논문에서 제안하는 회로는 CMOS 0.18 ㎛ 공정에서 설계되었으며, Active area가 5000㎛ X 5000㎛ 로 설계하였다. 동작 주파수는 1 ~ 1.5 MHz, 입력 전압 범위는 12V/5V이며, 출력 전압은 5.3V/1.1V이며, 각각 93.3%/93.8% 의 효율을 가진다.

주제어 : Multi-phase, Buck Converter, Inductor Current Balancing, Memory Interface

학번 : 2018-30775
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dc.description.abstractABSTRACT

Design of Multi-phase DC-DC Converter in Memory Inteface

In this thesis, design of multi-phase DC-DC buck converter in memory interface is proposed. Recently, as the amount of data memory used through IT devices through personal portable devices and laptops increases exponentially, cloud servers are being expanded, and accordingly, efficient, and stable power supply to all systems is essential. To satisfy these requirement, various types of DC-DC converters are being researched.
The proposed multi-phase DC-DC buck converter equally divides the high current into 4-phases to reduce the power loss that may occur due to the Ron resistor when the power MOSFET is turned on, and each phase is synchronous through a current balancing circuit. It is designed to work smoothly. In addition, the load transient response of voltage droop that can occur at the output stage due to the instant drive of the memory device can be quickly responded through the immediate current feedback from the output stage.
The circuit proposed in this paper was designed in a CMOS 0.18 ㎛ process, and the active area was designed as 5000㎛ X 5000㎛. The operating frequency is 1 ~ 1.5 MHz, the input voltage range is 12V/5V, the output voltage is 5.3V/1.1V, and the efficiency is 93.3%/93.8%, respectively.

Keywords : Multi-phase, Buck Converter, Inductor Current Balancing, Memory Interface

Student number: 2018-30775
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dc.description.tableofcontents1 Introduction . 1
2 Multi-phase buck converter의 feedback loop model 4
2.1 Conventional voltage mode. 4
2.2 Proposed Multi-phase Buck Converter 7
2.3 Ripple-based constant-on-time (COT) mode. 9
2.4 Voltage-controlled-oscillator (VCO)-based constant-on-time (COT) mode 14
2.4.1 Voltage-controlled-oscillator (VCO) Converter Scheme 14
2.4.2 Voltage-controlled-oscillator (VCO) Converter Current Feedback Scheme 16
2.5 Comparison of feedback loop models. 22
2.5.1 Conventional Voltage-mode Scheme 23
2.5.2 Ripple-based Feedback Scheme 24
2.5.3 Voltage Controlled Oscillator-Feedback Scheme 25
3 Multi-phase VCO-based COT buck converter design 26
3.1 The analysis of multi-phase VCO-based COT buck converter 26
3.1.1 Power Loss Analysis 26
3.1.2 Calculation of Inductor and Output Filter Capacitor 30
3.1.3 Continuous-Conduction-Mode (CCM) / Discontinuous-Conduction-Mode (DCM) 36
3.1.4 Loop gain analysis 39
3.1.5 Loop phase margin analysis. 42
3.1.6 Waveform of multi-phase VCO-based COT buck converter. 44
3.2 Design of transient response 47
3.2.1 Waveform of load transient response. 50
3.3 Design of inductor current balancing 53
3.3.1 Waveform of inductor current balancing response 53
3.3.1.1 Ripple-based inductor current balancing response. 53
3.3.1.2 VCO-based inductor current balancing response. 55
4 Measurement result. 57
4.1 PCB/microchip 57
4.1.1 PCB 57
4.2 Waveform. 60
4.2.1 Multi-phase DC-DC Buck Operation. 60
4.2.2 Efficiency 63
5 Conclusion and Future Work. 65
5.1 Conclusion 65
5.2 Future Work 67
5.2.1 Power Transistor 69
5.2.2 Inductor Zero Current Detection. 70
BIBLIOGRAPHY. 72
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dc.format.extentxi, 78-
dc.language.isokor-
dc.publisher서울대학교 대학원-
dc.subjectMulti-phase-
dc.subjectBuck Converter-
dc.subjectInductor Current Balancing-
dc.subjectMemory Interface-
dc.subject.ddc621.3-
dc.title메모리 인터페이스용 다중 위상 DC-DC 변환기 설계-
dc.title.alternativeDesign of Multi-phase DC-DC Converter in Memory Interface-
dc.typeThesis-
dc.typeDissertation-
dc.contributor.AlternativeAuthorJooyoung Chun-
dc.contributor.department공과대학 전기·정보공학부-
dc.description.degree박사-
dc.date.awarded2023-08-
dc.identifier.uciI804:11032-000000177702-
dc.identifier.holdings000000000050▲000000000058▲000000177702▲-
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