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TQSIM: A fast cycle-approximate processor simulator based on QEMU
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Shin-haeng | - |
dc.contributor.author | Yoo, Donghoon | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2023-12-11T06:44:40Z | - |
dc.date.available | 2023-12-11T06:44:40Z | - |
dc.date.created | 2018-08-29 | - |
dc.date.created | 2018-08-29 | - |
dc.date.created | 2018-08-29 | - |
dc.date.issued | 2016-05 | - |
dc.identifier.citation | Journal of Systems Architecture, Vol.66-67, pp.33-47 | - |
dc.identifier.issn | 1383-7621 | - |
dc.identifier.uri | https://hdl.handle.net/10371/198463 | - |
dc.description.abstract | Timing simulation of a processor is a key enabling technique to explore the design space of system architecture or to develop the software without an available hardware. We propose a fast cycle-approximate simulation technique for modern superscalar out-of-order processors. The proposed simulation technique is designed in two parts; the front-end provides correct functional execution of the guest application, and the back-end provides a timing model. For the back-end, we developed a novel processor timing model that combines a simple-formula-based analytical model and a scheduling analysis of sampled traces so as to boost up the simulation speed with minimal accuracy loss. Attached with a cache simulator, a branch predictor, and a trace analyzer, the proposed technique is implemented over the popular and portable QEMU emulator, so named TQSIM (Timed QEMU-based SIMulator). Sacrificing around 8 percent of the accuracy, TQSIM enables one or two orders of magnitude faster simulation than a reference cycle-accurate simulation when the target architecture is an ARM Cortex A15 processor. TQSIM is an open-source project currently available online. (C) 2016 Published by Elsevier B.V. | - |
dc.language | 영어 | - |
dc.publisher | Elsevier BV | - |
dc.title | TQSIM: A fast cycle-approximate processor simulator based on QEMU | - |
dc.type | Article | - |
dc.identifier.doi | 10.1016/j.sysarc.2016.04.012 | - |
dc.citation.journaltitle | Journal of Systems Architecture | - |
dc.identifier.wosid | 000378178700003 | - |
dc.identifier.scopusid | 2-s2.0-84964589084 | - |
dc.citation.endpage | 47 | - |
dc.citation.startpage | 33 | - |
dc.citation.volume | 66-67 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Ha, Soonhoi | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | PARALLEL SIMULATION | - |
dc.subject.keywordPlus | FRAMEWORK | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordAuthor | Superscalar out-of-order processor | - |
dc.subject.keywordAuthor | Analytical simulation | - |
dc.subject.keywordAuthor | Sampled simulation | - |
dc.subject.keywordAuthor | Cycle-approximate simulation | - |
dc.subject.keywordAuthor | QEMU | - |
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