An 82fs&lt;sub&gt;rms&lt;/sub&gt;-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS

Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk

doi:10.1109/ISSCC42613.2021.9365956

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An 82fs<sub>rms</sub>-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS

Cited 6 time in Web of Science Cited 12 time in Scopus

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Authors: Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk

Issue Date: 2021

Publisher: IEEE

Citation: 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.330-+

ISSN: 0193-6530

URI: https://hdl.handle.net/10371/199387

DOI: https://doi.org/10.1109/ISSCC42613.2021.9365956

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College of Engineering/Engineering Practice School (공과대학/대학원)
- Dept. of Electrical and Computer Engineering (전기·정보공학부)
  - Journal Papers (저널논문_전기·정보공학부)

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Choi, Jaehyouk최재혁: 부교수

College of Engineering
Department of Electrical and Computer Engineering

Research Area Wired interconnection, Wireless communication

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