A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator

Abstract

An injection-locked clock multiplier (ILCM) is one of the best options to generate low-jitter high-frequency signals, while using a ring VCO. In the sense that the VCO jitter is removed periodically by the reference clock, SREF, an MDLL also can be considered to be an ILCM. However, the most critical problem of ILCMs is that their jitter performance can degrade easily due to PVT. To ensure ultra-low jitter robustly, ILCMs must be equipped with background calibration that continuously adjusts the free-running frequency of the VCO, fVCO, to stay close to the target frequency, NfREF, where N is the multiplication factor and fREF is the frequency of SREF, thereby minimizing the frequency error. To date, various calibrating methods have been developed, and many of them [1]-[4] successfully tracked fVCO and prevented the degradation in random jitter, but none of the ILCMs succeeded in reducing reference spurs to a level comparable to that of PLLs. This is because even a slight phase error of an edge of the output signal, SOUT, could result in large reference spurs [1]. There are three major causes of the phase error, the first of which is the frequency error due to drifts in fVCO away from NfREF, which is the main target of prior calibrators. The second cause is the phase offset, which is generated due to any systematic errors of calibrators, such as mismatches in delay cells, input offsets of phase detectors, and limited resolution of digital circuits. Recently, state-of-the-art ILCMs [3], [4] successfully addressed these two causes, but they still could not reduce reference spurs to less than -65dBc. This is because, to date, none of the ILCMs has considered the third cause, i.e., the slope modulation of the edges of SOUT, which occurs due to the periodic injection of SREF.