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A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers

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dc.contributor.authorYoo, Seyeon-
dc.contributor.authorChoi, Seojin-
dc.contributor.authorKim, Juyeop-
dc.contributor.authorYoon, Heein-
dc.contributor.authorLee, Yongsun-
dc.contributor.authorChoi, Jaehyouk-
dc.date.accessioned2024-04-25T04:10:53Z-
dc.date.available2024-04-25T04:10:53Z-
dc.date.created2024-04-25-
dc.date.issued2018-02-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.2, pp.375-388-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://hdl.handle.net/10371/199407-
dc.description.abstractAn ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 mu W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was -129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were -39.1 dBc and 86 fs, respectively.-
dc.language영어-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers-
dc.typeArticle-
dc.identifier.doi10.1109/JSSC.2017.2749420-
dc.citation.journaltitleIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.wosid000423546800004-
dc.identifier.scopusid2-s2.0-85030682541-
dc.citation.endpage388-
dc.citation.number2-
dc.citation.startpage375-
dc.citation.volume53-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordPlusCLOCK MULTIPLIER-
dc.subject.keywordPlusPLL-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusSYNTHESIZER-
dc.subject.keywordPlusOSCILLATOR-
dc.subject.keywordAuthorCalibrator-
dc.subject.keywordAuthorfifth-generation (5G) transceivers-
dc.subject.keywordAuthorfrequency multiplier-
dc.subject.keywordAuthorfrequency-tracking loop (FTL)-
dc.subject.keywordAuthorinjection locked-
dc.subject.keywordAuthorintegrated phase noise (IPN)-
dc.subject.keywordAuthorprocess-voltage-temperature (PVT)-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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