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A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector
Cited 7 time in
Web of Science
Cited 8 time in Scopus
- Authors
- Issue Date
- 2018
- Publisher
- IEEE
- Citation
- ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.210-213
- Abstract
- This work presents a digital-analog-hybrid LDO (HLDO) using a multi-level gate-voltage generator (MGG) to achieve a small output ripple (Delta V-R) and a fast-transient response. Using the MGG that can partially turn on transistors in the power MOSFET (M-P) and thus reduce M-P's LSB current, Delta V-R was limited to less than 320 mu V. Also, a fast-decision PD detector having a non-zero decision level expedited the switching of transistors in MP, thereby reducing the settling time to less than 90 ns.
- ISSN
- 1930-8833
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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