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A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells
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Cited 11 time in Scopus
- Authors
- Issue Date
- 2015
- Publisher
- IEEE
- Citation
- 2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)
- Abstract
- This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than 4%.
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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