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A 45nm SOI-CMOS PLL with a Wideband LC-VCO

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dc.contributor.authorLee, Kun-Seok-
dc.contributor.authorBeck, Sungho-
dc.contributor.authorJeon, Hamhee-
dc.contributor.authorYoon, Youngchang-
dc.contributor.authorChoi, Jaehyouk-
dc.contributor.authorLee, Chang-Ho-
dc.contributor.authorKenney, J. Stevenson-
dc.date.accessioned2024-04-25T04:12:54Z-
dc.date.available2024-04-25T04:12:54Z-
dc.date.created2024-04-25-
dc.date.issued2011-
dc.identifier.citation2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)-
dc.identifier.issn1548-3746-
dc.identifier.urihttps://hdl.handle.net/10371/199446-
dc.description.abstractA 45nm SOI-CMOS PLL with a wideband LC-VCO is presented. The proposed PLL uses the advantage of SOI technology such as small parasitic capacitance and high Q-factor. The frequency range of the PLL is maximized because of a high maximum-to-minimum capacitance ratio of a capacitor bank. Measurement results show that the VCO generates 4.87-to-9.65GHz frequency signals with 65.8% frequency coverage. Fabricated chip occupies 0.09mm2 of active area and consumes less than 7mA current from single 1.0V supply.-
dc.language영어-
dc.publisherIEEE-
dc.titleA 45nm SOI-CMOS PLL with a Wideband LC-VCO-
dc.typeArticle-
dc.citation.journaltitle2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)-
dc.identifier.wosid000296057200011-
dc.identifier.scopusid2-s2.0-80053650043-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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