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A robust latch-type sense amplifier using adaptive latch resistance

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dc.contributor.authorSong, Taejoong-
dc.contributor.authorLee, Sang Min-
dc.contributor.authorChoi, Jaehyouk-
dc.contributor.authorKim, Stephen-
dc.contributor.authorKim, Gyuhong-
dc.contributor.authorLim, Kyutae-
dc.contributor.authorLaskar, Joy-
dc.date.accessioned2024-04-25T04:13:03Z-
dc.date.available2024-04-25T04:13:03Z-
dc.date.created2024-04-25-
dc.date.issued2010-
dc.identifier.citation2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp.182-185-
dc.identifier.urihttps://hdl.handle.net/10371/199449-
dc.description.abstractA latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.-
dc.publisherIEEE-
dc.titleA robust latch-type sense amplifier using adaptive latch resistance-
dc.typeArticle-
dc.identifier.doi10.1109/ICICDT.2010.5510258-
dc.citation.journaltitle2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010-
dc.identifier.scopusid2-s2.0-77955618689-
dc.citation.endpage185-
dc.citation.startpage182-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Jaehyouk-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.subject.keywordAuthorBit-cell-
dc.subject.keywordAuthorLatch sense amplifier-
dc.subject.keywordAuthorLeakage current-
dc.subject.keywordAuthorSRAM-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Wired interconnection, Wireless communication

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