Subthreshold Current Mode Matrix Determinant Computation for Analog Signal Processing

Abstract

The matrix determinant computation system (MDCS) is developed in subthreshold current-mode for an analog signal processing. By utilizing the translinear loop principle and the novel differential architecture, the MDCS can perform accurate addition, subtraction, and multiplication in analog domain. The system computes a 2-by-2 and 3-by-3 determinant with 91% accuracy and a 3 kHz input can be handled while consuming 110.05 mu W. The overall system is fabricated on a 0.18 mu m CMOS technology and the area is 500 mu m x 800 mu m.