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High multiplication factor capacitor multiplier for an on-chip PLL loop filter
Cited 29 time in
Web of Science
Cited 33 time in Scopus
- Authors
- Issue Date
- 2009-02
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, Vol.45 No.5, pp.239-U8
- Abstract
- A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 mu A. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 mu m CMOS technology to employ the proposed capacitor multiplier.
- ISSN
- 0013-5194
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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