A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver

Abstract

A 180-GHz minimum shift keying (MSK) receiver (RX) using a phase-locked loop (PLL), which self-synchronizes the carrier frequency, is demonstrated. The mixer-first RX is fabricated in a 65-nm CMOS process. A double-balanced anti-parallel-diode-pair sub-harmonic mixer performs the phase detection, reducing the frequency of local oscillator (LO) by half. Tunable zeros realized by series inductors are used to improve the stability and to increase the data rate handling capability. Without external LO synchronization, the RX demodulates MSK signals at 10 Gb/s with a bit error rate (BER) < 10(-12) and at the maximum data rate of 12.5 Gb/s with a BER of 3.8 x 10(-5). The BER at 10 Gb/s is the lowest and the data rate of 12.5 Gb/s is the highest fir PLL RXs.