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A 40fJ/c-s 1 V 10 bit SARADC with Dual Sampling Capacitive DAC Topology
Cited 4 time in
Web of Science
Cited 6 time in Scopus
- Authors
- Issue Date
- 2011-03
- Publisher
- 대한전자공학회
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.11 No.1, pp.23-32
- Abstract
- A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 mu m 1P6M CMOS technology and occupies 1.17 mm(2) including pads. It dissipates only 1.1 mu W with 1 V supply voltage while operating at 100 kS/s.
- ISSN
- 1598-1657
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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