Publications
Detailed Information
An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC
Cited 9 time in
Web of Science
Cited 12 time in Scopus
- Authors
- Issue Date
- 2009-05
- Publisher
- IEEE
- Citation
- IEEE International Symposium on Circuits and Systems proceedings, pp.972-975
- Abstract
- This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced by 68% compared with conventional SAR ADC. Moreover, switching energy distribution is more uniform over entire output code compared with previous works.
- ISSN
- 0271-4302
- Files in This Item:
- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.