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An embedded 8-bit RISC controller for yield enhancement of the 90-nm PRAM
Cited 1 time in
Web of Science
Cited 0 time in Scopus
- Authors
- Issue Date
- 2007-09
- Publisher
- IEEE
- Citation
- PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, p. 4405847
- Abstract
- An embedded 8b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100MHz and consumes 28.4mW at 1.0V supply voltage. The embedded RISC enables 100Mb/s/pin read/write throughputs to PRAM.
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Related Researcher
- Yoo, Jerald유담
- 부교수
- College of Engineering
- Department of Electrical and Computer Engineering
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