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A 10-μW digital signal processor with adaptive-SNR monitoring for a sub-IV digital hearing aid
Cited 3 time in
Web of Science
Cited 4 time in Scopus
- Authors
- Issue Date
- 2006
- Publisher
- IEEE
- Citation
- IEEE International Symposium on Circuits and Systems proceedings, pp.3361-3364
- Abstract
- An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 mu W at sub-1V. The DSP consumes only 10 mu W at 0.9-V single supply, and occupies 0.3 mm(2) with gate count of 10k using 0.18-mu m CMOS process.
- ISSN
- 0271-4302
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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