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FARNN: FPGA-GPU Hybrid Acceleration Platform for Recurrent Neural Networks

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dc.contributor.authorCho, Hyungmin-
dc.contributor.authorLee, Jeesoo-
dc.contributor.authorLee, Jaejin-
dc.date.accessioned2024-05-03T07:36:31Z-
dc.date.available2024-05-03T07:36:31Z-
dc.date.created2021-12-14-
dc.date.issued2022-07-01-
dc.identifier.citationIEEE Transactions on Parallel and Distributed Systems, Vol.33 No.7, pp.1725-1738-
dc.identifier.issn1045-9219-
dc.identifier.urihttps://hdl.handle.net/10371/200911-
dc.description.abstractGPU-based platforms provide high computation throughput for large mini-batch deep neural network computations. However, a large batch size may not be ideal for some situations, such as aiming at low latency, training on edge/mobile devices, partial retraining for personalization, and having irregular input sequence lengths. GPU performance suffers from low utilization especially for small-batch recurrent neural network (RNN) applications where sequential computations are required. In this article, we propose a hybrid architecture, called FARNN, which combines a GPU and an FPGA to accelerate RNN computation for small batch sizes. After separating RNN computations into GPU-efficient and GPU-inefficient tasks, we design special FPGA computation units that accelerate the GPU-inefficient RNN tasks. FARNN off-loads the GPU-inefficient tasks to the FPGA. We evaluate FARNN with synthetic RNN layers of various configurations on the Xilinx UltraScale+ FPGA and the NVIDIA P100 GPU in addition to evaluating it with real RNN applications. The evaluation result indicates that FARNN outperforms the P100 GPU platform for RNN training by up to 4.2x with small batch sizes, long input sequences, and many RNN cells per layer.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleFARNN: FPGA-GPU Hybrid Acceleration Platform for Recurrent Neural Networks-
dc.typeArticle-
dc.identifier.doi10.1109/TPDS.2021.3124125-
dc.citation.journaltitleIEEE Transactions on Parallel and Distributed Systems-
dc.identifier.wosid000719558900002-
dc.identifier.scopusid2-s2.0-85118639502-
dc.citation.endpage1738-
dc.citation.number7-
dc.citation.startpage1725-
dc.citation.volume33-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorLee, Jaejin-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordAuthorFPGA-
dc.subject.keywordAuthorGPU-
dc.subject.keywordAuthorhybrid platform-
dc.subject.keywordAuthorRNN-
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