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A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS
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Cited 5 time in Scopus
- Authors
- Issue Date
- 2015-08
- Citation
- IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353
- Abstract
- A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10(-12) while operating at 14Gb/s with 12dB channel loss.
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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