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A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
Cited 100 time in
Web of Science
Cited 110 time in Scopus
- Authors
- Issue Date
- 2015-04
- Citation
- IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.867-881
- Abstract
- A digital fractional-N PLL that employs a high resolution TDC and a truly Delta Sigma fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out Delta Sigma quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs(rms) integrated jitter. This translates to a FoM(J) of -240.5 dB, which is the best among the reported fractional-N PLLs.
- ISSN
- 0018-9200
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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