Publications
Detailed Information
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC
Cited 0 time in
Web of Science
Cited 8 time in Scopus
- Authors
- Issue Date
- 2014-06
- Citation
- IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858391
- Abstract
- A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than-106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoM J of-240.5dB, which is the best among the reported fractional-N PLLs. © 2014 IEEE.
- Files in This Item:
- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.