A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

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A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Cited 0 time in Web of Science Cited 7 time in Scopus

Authors: Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo-Seok; Elshazly, Amr; Hanumolu, Pavan Kumar

Citation: IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858446

Abstract: A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of-104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of-225.8dB. © 2014 IEEE.