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Graphene based heterostructures

Cited 182 time in Web of Science Cited 189 time in Scopus
Authors

Dean, C.; Young, A. F.; Wang, L.; Meric, I.; Lee, G. -H.; Watanabe, K.; Taniguchi, T.; Shepard, K.; Kim, P.; Hone, J.

Issue Date
2012-08
Publisher
Elsevier BV
Citation
Solid State Communications, Vol.152 No.15, pp.1275-1282
Abstract
The two dimensional charge carriers in monolayer and bilayer graphene are described by massless and massive chiral Dirac Hamiltonians, respectively. These two-dimensional materials are predicted to exhibit a wide range of behavior, etc. However, graphene devices on a typical three-dimensional insulating substrates such as SiO2 are highly disordered, exhibiting characteristics that are far inferior to the expected intrinsic properties of graphene. We have developed a novel technique for substrate engineering of graphene devices using layered dielectric materials to build graphene based vertical heterostructures. We employ hBN, an insulating isomorph of graphite, as a substrate and gate dielectric for graphene electronics. In this review, we describe the fabrication and characterization of high-quality exfoliated mono- and bilayer graphene devices on single-crystal hBN substrates, using a mechanical transfer process. Graphene devices on hBN substrates have mobilities and carrier inhomogeneities that are almost an order of magnitude better than devices on SiO2. We use the enhanced mobility of electrons in hBN supported graphene to investigate the effects of electronic interactions. We find that interactions drive spontaneous breaking of the emergent SU(4) symmetry of the graphene Landau levels, leading to a variety of non-trivial integer and fractional quantum Hall states. The ability to assemble crystalline layered materials in a controlled way permits the fabrication of graphene devices on other promising dielectrics and allows for the realization of more complex graphene heterostructures. (c) 2012 Elsevier Ltd. All rights reserved.
ISSN
0038-1098
URI
https://hdl.handle.net/10371/203538
DOI
https://doi.org/10.1016/j.ssc.2012.04.021
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  • College of Engineering
  • Department of Materials Science & Engineering
Research Area 2D materials, 2차원 물질, Smiconductor process, semiconductor devices, 반도체 공정, 반도체 소자

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