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A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems
Cited 44 time in
Web of Science
Cited 61 time in Scopus
- Authors
- Issue Date
- 1999
- Citation
- IEEE J. Solid-State Circuits, vol. 34, pp. 898-903
- Keywords
- Adiabatic circuit ; carry-lookahead adder ; clocked ; reversible energy recovery logic ; self-energyrecovery
- Abstract
- In this paper, we describe an energy-efficient carrylookahead
adder using reversible energy recovery logic (RERL),
which is a new dual-rail reversible adiabatic logic. We also
describe an eight-phase, clocked power generator that requires
an off-chip inductor. For the energy-efficient design of reversible
logic, we explain how to control the overhead of reversibility with
a self-energy-recovery circuit. A test chip was implemented with
a 0.8- m CMOS technology, which included two 16-bit carrylookahead
adders to allow fair comparison: an RERL one and a
static CMOS one. Experimental results showed that the RERL
adder had substantial advantages in energy consumption over the
static CMOS one at low operating frequencies. We also confirmed
that we could minimize the energy consumption in the RERL
circuit by reducing the operating frequency until adiabatic and
leakage losses were equal.
- ISSN
- 0018-9200
- Language
- English
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