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Low-jitter design techniques of fractional-N frequency systhesizers using multi-phase clocks : 다중위상 클럭을 이용한 저 잡음 주파수 합성기의 설계
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- Authors
- Advisor
- 정덕균
- Issue Date
- 2006
- Publisher
- 서울대학교 대학원
- Keywords
- Phase-locked loop (PLL) ; Phase-locked loop (PLL) ; all digital PLL (ADPLL) ; all digital PLL (ADPLL) ; hybrid PLL ; hybrid PLL ; fractional-N ; fractional-N ; EMI ; EMI ; spread spectrum clocking (SSC) ; spread spectrum clocking (SSC) ; multiphase clock ; multiphase clock ; ΔΣ modulator ; ΔΣ modulator ; digitally controlled oscillator (DCO). ; digitally controlled oscillator (DCO).
- Description
- Thesis(doctoral)--서울대학교 대학원 :전기·컴퓨터공학부,2006.
- Language
- English
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000046580
https://hdl.handle.net/10371/45366
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