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(A) study on design of all-digital phase-locked loop : All-digital PLL 설계에 관한 연구
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 정덕균 | - |
| dc.contributor.author | 오도환 | - |
| dc.date.accessioned | 2010-01-29T06:08:30Z | - |
| dc.date.available | 2010-01-29T06:08:30Z | - |
| dc.date.copyright | 2009. | - |
| dc.date.issued | 2009 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038196 | eng |
| dc.identifier.uri | https://hdl.handle.net/10371/46839 | - |
| dc.description | Thesis(doctors) --서울대학교 대학원 :전기· 컴퓨터공학부,2009.8. | en |
| dc.format.extent | iv, 100 leaves | en |
| dc.language.iso | en | en |
| dc.publisher | 서울대학교 대학원 | en |
| dc.subject | 클럭-데이터 복원기 | en |
| dc.subject | ADPLL | en |
| dc.subject | 주파수합성기 | en |
| dc.subject | Clock-and-Data Recovery | en |
| dc.subject | 지터 | en |
| dc.subject | Frequency Synthesizer | en |
| dc.subject | 위상잡음 | en |
| dc.subject | Jitter | en |
| dc.subject | Phase noise | en |
| dc.subject | Time-to-Digital Converter | en |
| dc.subject | Digitally-Controlled Oscillator | en |
| dc.title | (A) study on design of all-digital phase-locked loop | en |
| dc.title.alternative | All-digital PLL 설계에 관한 연구 | en |
| dc.type | Thesis | - |
| dc.contributor.department | 전기· 컴퓨터공학부 | - |
| dc.description.degree | Doctor | en |
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