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Power reduction in look-up table based FPGAs by glitch minimization

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Authors
임현민
Advisor
장래혁
Issue Date
2005
Publisher
서울대학교 대학원
Keywords
FPGA저전력power-reduction최적화optimizationNP-completeNP-complete시뮬레이션simulation
Description
Thesis(master`s)--서울대학교 대학원 :전기.컴퓨터공학부,2005.
Language
English
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000052883

http://hdl.handle.net/10371/50027
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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