Clock generation circuit with all-digital PLL

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Clock generation circuit with all-digital PLL : 디지털 PLL을 이용한 clock 발생용 회로에 관한 연구

DC Field	Value	Language
dc.contributor.advisor	정덕균	-
dc.contributor.author	안현석	-
dc.date.accessioned	2010-02-09	-
dc.date.available	2010-02-09	-
dc.date.copyright	2007.	-
dc.date.issued	2007	-
dc.identifier.uri	http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043911	kog
dc.identifier.uri	https://hdl.handle.net/10371/52469	-
dc.description	학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.	ko
dc.format.extent	ii, 54 장	ko
dc.language.iso	ko	ko
dc.publisher	서울대학교 대학원	ko
dc.subject	All -digital PLL(ADPLL)	ko
dc.subject	All -digital PLL	ko
dc.subject	DCO(Digitally Controlled Oscillator)	ko
dc.subject	Digitally Controlled Oscillator	ko
dc.subject	TDC(Time-to-Digital Converter)	ko
dc.subject	Time-to-Digital Converter	ko
dc.subject	Delta-Sigma Modulator	ko
dc.subject	Delta-Sigma Modulator	ko
dc.subject	위상잡음	ko
dc.subject	Phase noise	ko
dc.subject	Jitter	ko
dc.title	Clock generation circuit with all-digital PLL	ko
dc.title.alternative	디지털 PLL을 이용한 clock 발생용 회로에 관한 연구	ko
dc.type	Thesis	-
dc.contributor.department	전기. 컴퓨터공학부	-
dc.description.degree	Master	ko

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