Browse

Packing Buffer for Efficient Irregular Data access in SIMD Processors

DC Field Value Language
dc.contributor.authorChang, Hoseok-
dc.contributor.authorLim, Jieun-
dc.contributor.authorSung, Wonyong-
dc.date.accessioned2009-08-04T06:45:45Z-
dc.date.available2009-08-04T06:45:45Z-
dc.date.issued2009-
dc.identifier.citation제16회 한국반도체학술대회en
dc.identifier.urihttp://kcs.cosar.or.kr-
dc.identifier.urihttp://hdl.handle.net/10371/6141-
dc.description.abstractThe performance of an SIMD (Single Instruction Multiple Data) processor is bounded by the memory bottleneck; most of which is due to the overhead for preparing aligned vector data. In this paper, we have added a hardware unit to an SIMD processor to reduce the alignment overhead. The proposed packing buffer contains a small size multi-port memory block for which multiple addresses are generated by using a vector index register. Since the packing buffer has a small size, it requires neither complex hardware nor increased CPU cycle time. DSP benchmarks are used to measure the performance efficiency.en
dc.description.sponsorship이 논문은 지식경제부 출연금으로 ETRI와 시스템반도체산업진흥센터에서 수행한 IT SoC 핵심설계인력양성사업, 그리고 삼성반도체 주식회사의 지원을 받아 수행한 연구결과입니다.en
dc.language.isokoen
dc.titlePacking Buffer for Efficient Irregular Data access in SIMD Processorsen
dc.typeConference Paperen
dc.contributor.AlternativeAuthor장호석-
dc.contributor.AlternativeAuthor임지은-
dc.contributor.AlternativeAuthor성원용-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
Files in This Item:
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse