SHERP

VLSI implementation of a soft bit-flipping decoder for PG-LDPC codes

Cited 0 time in webofscience Cited 2 time in scopus
Authors
Cho, Junho; Kim, Jonghong; Ji, Hyunwoo; Sung, Wonyong
Issue Date
2009-05
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE International Symposium on Circuits and Systems (ISCAS), pp. 908-911, May 2009
Abstract
Implementation of high throughput VLSI chips for low-density parity-check codes has been considered very difficult especially when the row or column weight of the code is high. In this paper, a projective-geometry (PG) LDPC code is implemented in VLSI employing the proposed soft bit flipping (SBF) algorithm. The SBF algorithm requires only simple interconnections, but its error correcting performance is close to the sum-product algorithm (SPA). Parallel processing architecture is employed for increasing the throughput. With the (1057, 813) PG-LDPC code, the implemented 4-bit SBF decoder consumes only a small area of 2.5mm2 while providing 6.5Gbps and good performance close to the floating-point SPA by 0.6dB at the frame error rate of 10-4.
Language
English
URI
http://www.iscas2009.org

http://hdl.handle.net/10371/6166
DOI
https://doi.org/10.1109/ISCAS.2009.5117904
Files in This Item:
There are no files associated with this item.
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse