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Hardware implementation of inter-processor communication in MPSoCs for multimedia applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Koo, Moonmo | - |
| dc.contributor.author | Chae, Soo-Ik | - |
| dc.date.accessioned | 2010-04-01T02:00:46Z | - |
| dc.date.available | 2010-04-01T02:00:46Z | - |
| dc.date.issued | 2007-07 | - |
| dc.identifier.citation | International Technical Conference on Circuits/Systems, Computers and Communications | en |
| dc.identifier.uri | https://hdl.handle.net/10371/62296 | - |
| dc.description.abstract | In this paper we present a scalable and flexible architecture
that implements inter-processor communication (IPC) synchronization among FIFO channels for multimedia applications. We also compare it to the simple mail-box architecture, especially for tasks of finer granularity. With experimental results we confirmed the proposed architecture is suitable for various cases including a Motion JPEG example. | en |
| dc.language.iso | en | en |
| dc.title | Hardware implementation of inter-processor communication in MPSoCs for multimedia applications | en |
| dc.type | Conference Paper | en |
| dc.contributor.AlternativeAuthor | 구문모 | - |
| dc.contributor.AlternativeAuthor | 채수익 | - |
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