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A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Suhwan | - |
| dc.contributor.author | Stephen V., Kosonocky | - |
| dc.contributor.author | Daniel R, Knebel | - |
| dc.contributor.author | Kevin, Stawiasz | - |
| dc.contributor.author | Marios C, Papaefthymiou | - |
| dc.date.accessioned | 2010-06-29T23:55:26Z | - |
| dc.date.available | 2010-06-29T23:55:26Z | - |
| dc.date.issued | 2007-07 | - |
| dc.identifier.citation | IEEE Transactions on Circuits and Systems Part 2 Express Briefs, vol. 54, no. 7, pp. 586-590 | en |
| dc.identifier.issn | 1549-7747 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/68015 | - |
| dc.description.abstract | Most existing power gating structures provide only
one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate powersaving and data-retaining mode. Experiments with test structures fabricated in 0.13- mCMOSbulk technology showthat our power gating structure yields an expanded design space with more powerperformance tradeoff alternatives. | en |
| dc.language.iso | en | en |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.subject | Deep-submicrometer CMOS | en |
| dc.subject | ground bounce noise | en |
| dc.subject | low voltage | en |
| dc.subject | multi-threshold CMOS (MTCMOS) | en |
| dc.title | A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 김수환 | - |
| dc.identifier.doi | 10.1109/TCSII.2007.894428 | - |
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