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Fast-locking CDR circuit with autonomously reconfigurable mechanism
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Woo, Jong-Kwan | - |
| dc.contributor.author | Jeong, Deong-Kyoon | - |
| dc.contributor.author | Kim, Suhwan | - |
| dc.date.accessioned | 2010-07-06T05:57:18Z | - |
| dc.date.available | 2010-07-06T05:57:18Z | - |
| dc.date.issued | 2007-05-24 | - |
| dc.identifier.citation | Electronics Letters- IEE, 2007, 43(11):624 | en |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/68318 | - |
| dc.description.abstract | A new fast-locking scheme is applied to a clock and data recovery
(CDR) circuit based on a phase-locked loop. Locking time is reduced by using an autonomously reconfigurable charge pump and loop filter. A 1.25 Gbit=s prototype CDR circuit has been implemented in a 0.18 mm CMOS technology. | en |
| dc.language.iso | en | en |
| dc.publisher | Institution of Engineering and Technology | en |
| dc.title | Fast-locking CDR circuit with autonomously reconfigurable mechanism | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 우종관 | - |
| dc.contributor.AlternativeAuthor | 정덕균 | - |
| dc.contributor.AlternativeAuthor | 김수환 | - |
| dc.identifier.doi | 10.1049/el:20070036 | - |
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