Publications
Detailed Information
True single-phase adiabatic circuitry
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Suhwan | - |
dc.contributor.author | Papaefthymiou, Marios C. | - |
dc.date.accessioned | 2010-11-08T22:10:25Z | - |
dc.date.available | 2010-11-08T22:10:25Z | - |
dc.date.issued | 2001-02 | - |
dc.identifier.citation | IEEE Transactions on Very Large Scale Integration Systems, vol. 9, pp. 52-63 | en |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://hdl.handle.net/10371/70059 | - |
dc.description.abstract | Dynamic logic families that rely on energy recovery
to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme.We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 m standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our 8-bit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Adiabatic circuits | en |
dc.subject | carry-lookahead adder | en |
dc.title | True single-phase adiabatic circuitry | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김수환 | - |
dc.identifier.doi | 10.1109/92.920819 | - |
- Appears in Collections:
- Files in This Item:
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.